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? semiconductor components industries, llc, 2002 april, 2002 rev. 4 1 publication order number: mc10e136/d mc10e136, mc100e136 5vecl 6bit universal up/down counter the mc10e/100e136 is a 6-bit synchronous, presettable, cascadable universal counter. the device generates a look-ahead-carry output and accepts a look-ahead-carry input. these two features allow for the cascading of multiple e136's for wider bit width counters that operate at very nearly the same frequency as the stand alone counter. the clout output will pulse low for one clock cycle one count before the e136 reaches terminal count. the cout output will pulse low for one clock cycle when the counter reaches terminal count. for more information on utilizing the look-ahead-carry features of the device please refer to the applications section of this data sheet. the differential cout output facilitates the e136's use in programmable divider and self-stopping counter applications. unlike the h136 and other similar universal counter designs the e136 carry out and look-ahead-carry out signals are registered on chip. this design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. because of this architecture there are some minor functional differences between the e136 and h136 counters. the user, regardless of familiarity with the h136, should read this data sheet carefully. note specifically (see logic diagram) the operation of the carry out outputs and the look-ahead-carry in input when utilizing the master reset. when left open all of the input pins will be pulled low via an input pulldown resistor. the master reset is an asynchronous signal which when asserted will force the q outputs low. the q outputs need not be terminated for the e136 to function properly, in fact if these outputs will not be used in a system it is recommended to save power and minimize noise that they be left open. this practice will minimize switching noise which can reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system. the 100 series contains temperature compensation. ? 550 mhz count frequency ? fully synchronous up and down counting ? look-ahead-carry input and output ? asynchronous master reset ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 2 kv hbm, > 100 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 506 devices device package shipping ordering information mc10e136fn plcc28 37 units/rail mc10e136fnr2 plcc28 500 units/reel mc100e136fn plcc28 37 units/rail mc100e136fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e136fn awlyyww mc100e136fn awlyyww http://onsemi.com 128 128
mc10e136, mc100e136 http://onsemi.com 2 pin names pin function d 0 d 5 ecl preset data inputs q 0 q 5 ecl data outputs s1, s2 mode control pins mr master reset clk ecl clock input cout , cout ecl differential carry-out output (active low) clout ecl look-ahead-carry out (active low) cin ecl carry-in input (active low) clin ecl look-ahead-carry in input (active low) v cc , v cco positive supply v ee negative supply function table ( expanded truth table on page 5) s1 s2 cin mr clk function l l l h h h x l h h l l h x x l h l h x x l l l l l l h z z z z z z x preset parallel data increment (count up) hold count decrement (count down) hold count hold count reset (qn = low) e136 universal up/down counter logic diagram s1 s2 cin clin mr clk dq s dq r q dq r q dq r q dq s q dq s d0 q0 d1 q1 d2 - d4 q2 - q4 d5 q5 cout qm0 qm1 qm0 cout clout bits 2 - 4 note that this diagram is provided for understanding of logic operation only. it should not be used for propagation delays as m any gate functions are achieved internally without incurring a full gate delay. d0 d3 d4 d5 v cco q5 q4 v cco q3 q2 v cc v cco cout cout clout v cco q1 q0 v cco d1 mr clin cin clk v ee s1 s2 d2 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 8 6 5 pinout: 28-lead plcc (top view) * all v cc and v cco pins are tied together on the die. logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation.
mc10e136, mc100e136 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 125 150 125 150 125 150 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 125 150 125 150 125 150 ma v oh output high voltage (note 2) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 2) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc10e136, mc100e136 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 125 150 125 150 140 170 ma v oh output high voltage (note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 125 150 125 150 140 170 ma v oh output high voltage (note 2) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f count maximum count frequency 550 650 e 550 650 e 550 650 e mhz t plh t phl propagation delay to output clk to q mr to q clk to cout clk to clout 850 850 800 825 1150 1150 1150 1150 1450 1450 1300 1400 850 850 800 825 1150 1150 1150 1150 1450 1450 1300 1400 850 850 800 825 1150 1150 1150 1150 1450 1450 1300 1400 ps t s setup time s1, s2 d clin cin 1000 800 150 800 650 400 0 400 e e e e 1000 800 150 800 650 400 0 400 e e e e 1000 800 150 800 650 400 0 400 e e e e ps t h hold time s1, s2 d clin cin 150 150 300 150 200 250 0 250 e e e e 150 150 300 150 200 250 0 250 e e e e 150 150 300 150 200 250 0 250 e e e e ps t rr reset recovery time 1000 700 e 1000 700 e 1000 700 e ps t jitter cycletocycle jitter tbd tbd tbd ps t pw minimum pulse width clk, mr 700 400 e 700 400 e 700 400 e ps t r t f rise/fall times 20% - 80% cout other 275 300 e e 600 700 275 300 e e 600 700 275 300 e e 600 700 ps 1. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v.
mc10e136, mc100e136 http://onsemi.com 5 expanded truth table function s1 s2 mr cin clin clk d5 d4 d3 d2 d1 d0 q5 q4 q3 q2 q1 q0 cout clout preset l l l x x z l l l l h h l l l l h h h h down h h h h l l l l l l l l l l l l l l l l z z z z x x x x x x x x x x x x x x x x x x x x x x x x l l l h l l l h l l l h l l l h h l l h l h l h h h l h h l h h preset l l l x x z h h h h l l h h h h l l h h up l l l l l l h h h h h h l l l l l l l l l l l l l l l l l l z z z z z z x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x h h h l l l h h h l l l h h h l l l h h h l l l l h h l l h h l h l h l h h l h h h h l h h h h hold h h h h l l x x x x z z x x x x x x x x x x x x l l l l l l l l h h l l h h h h down hold down hold hold h h h h h h h h l l l l l l l l l l l l l l l l l h l h h h l l l l l l l h h l z z z z z z z z x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l h h l l l l l l h h l h h h l l l h h h h h h h hold preset up hold up hold hold h l l l l l l l l h l h h h h h h h l l l l l l l l l l x l l h l h h l l x l l l l l h l z z z z z z z z z x h x x x x x x x x h x x x x x x x x h x x x x x x x x h x x x x x x x x l x x x x x x x x l x x x x x x x l h h h h h h h h l h h h h h h h h l h h h h h h h h l h h h h h h h h l l l h h h h h h l l h l l h h h h l h h h h l h h l h h h l h h h h h up l l l l h h h h l l l l l l l l l l l l z z z z x x x x x x x x x x x x x x x x x x x x x x x x l l l l l l l l l l l l l l l l l l h h l h l h h h h h h h h h reset x x h x x x x x x x x x l l l l l l h h z = low to high transition
mc10e136, mc100e136 http://onsemi.com 6 applications information overview the mc10e/100e136 is a 6-bit synchronous, presettable, cascadable universal counter. using the s1 and s2 control pins the user can select between preset, count up, count down and hold count. the master reset pin will reset the internal counter, and set the cout , clout , and clin flip-flops. unlike previous 136 type counters the carry out outputs will go to a high state during the preset operation. in addition since the carry out outputs are registered they will not go low if terminal count is loaded into the register. the look-ahead-carry out output functions similarly. note from the schematic the use of the master information from the least significant bits for control of the two carry out functions. this architecture not only reduces the carry out delay, but is essential to incorporate the registered carry out functions. in addition to being faster, because these functions are registered the resulting carry out signals are stable and glitch free. cascading multiple e136 devices many applications require counters significantly larger than the 6 bits available with the e136. for these applications several e136 devices can be cascaded to increase the bit width of the counter to meet the needs of the application. in the past cascading several 136 type universal counters necessarily impacted the maximum count frequency of the resulting counter chain. this performance impact was the result of the terminal count signal of the lower order counters having to ripple through the entire counter chain. as a result past counters of this type were not widely used in large bit counter applications. an alternative counter architecture similar to the e016 binary counter was implemented to alleviate the need to ripple propagate the terminal count signal. unfortunately these types of counters require external gating for cascading designs of more than two devices. in addition to requiring additional components, these external gates limit the cascaded count frequency to a value less than the free running count frequency of a single counter. although there is a performance impact with this type of architecture it is minor compared to the impact of the ripple propagate designs. as a result the e016 type counters have been used extensively in applications requiring very high speed, wide bit width synchronous counters. on semiconductor has incorporated several improvements to past universal counter designs in the e136 universal counter. these enhancements make the e136 the unparalleled leader in its class. with the addition of look-ahead-carry features on the terminal count signal, very large counter chains can be designed which function at very nearly the same clock frequency as a single free running device. more importantly these counter chains require no external gating. figure 1 below illustrates the interconnect scheme for using the look-ahead-carry features of the e136 counter. figure 1. 24-bit cascaded e136 counter q0 > q5 d0 > d5 clk q0 > q5 d0 > d5 clk q0 > q5 d0 > d5 clk lsb q0 > q5 d0 > d5 clout cout clin cin clk clout cout clk 000001 000000 111111 111110 111101 clock aloo aloo aloo clout cout clin cin clout cout clin cin msb clout cout clin cin
mc10e136, mc100e136 http://onsemi.com 7 figure 2. look-ahead-carry input structure active low clk cin clin q d note from the waveforms that the look-ahead-carry output (clout ) pulses low one clock pulse before the counter reaches terminal count. also note that both clout and the carry out pin (cout ) of the device pulse low for only one clock period. the input structure for look-ahead-carry in (clin ) and carry in (cin ) is pictured in figure 2. the clin input is registered and then ored with the cin input. from the truth table one can see that both the cin and the clin inputs must be in a low state for the e136 to be enabled to count (either count up or count down). the clin inputs are driven by the clout output of the lowest order e136 and therefore are only asserted for a single clock period. since the clin input is registered it must be asserted one clock period prior to the cin input. if the counter previous to a given counter is at terminal count its cout output and thus the cin input of the given counter will be in the alowo state. this signals the given counter that it will need to count one upon the next terminal count of the least significant counter (lsc). the clout output of the lsc will pulse low one clock period before it reaches terminal count. this clout signal will be clocked into the clin input of the higher order counters on the following positive clock transition. since both cin and clin are in the low state the next clock pulse will cause the least significant counter to roll over and all higher order counters, if signaled by their cin inputs, to count by one. figure 3. 6-bit programmable divider aloo s2 s1 q0 > q5 d0 > d5 cout cout clk clock during the clock pulse in which the higher order counter is counting by one the clin is clocking in the high signal presented by the clout of the lsc. the cin 's in the higher order counter will ripple propagate through the chain to update the count status for the next occurrence of terminal count on the lsc. this ripple propagation will not af fect the count frequency as it has 2 6 1 or 63 clock pulses to ripple through without affecting the count operation of the chain. the only limiting factor which could reduce the count frequency of the chain as compared to a free running single device will be the setup time of the clin input. this limit will consist of the clk to clout delay of the e136 plus the clin setup time plus any path length differences between the clout output and the clock. programmable divider using external feedback of the cout pin, the e136 can be configured as a programmable divider. figure 3 illustrates the configuration for a 6-bit count down programmable divider. if for some reason a count up divider is preferred the cout signal is simply fed back to s2 rather than s1. examination of the truth table for the e136 shows that when both s1 and s2 are low the counter will parallel load on the next positive transition of the clock. if the s2 input is low and the s1 input is high the counter will be in the count down mode and will count towards an all zero state upon successive clock pulses. knowing this and the operation of the cout output it becomes a trivial matter to build programmable dividers. for a programmable divider one wants to load a predesignated number into the counter and count to terminal count. upon terminal count the counter should automatically reload the divide number. with the architecture shown in figure 3 when the counter reaches terminal count the cout output and thus the s1 input will go low, this combined with the low on s2 will cause the counter to load the inputs present on d0-d5. upon loading the divide value into the counter cout will go high as the counter is no longer at terminal count thereby placing the counter back into the count mode. table 1. preset inputs versus divide ratio divide preset data inputs ratio d5 d4 d3 d2 d1 d0 2 3 4 5 ? ? 36 37 38 ? ? 62 63 64 l l l l ? ? h h h ? ? h h h l l l l ? ? l l l ? ? h h h l l l l ? ? l l l ? ? h h h l l l h ? ? l h h ? ? h h h l h h l ? ? h l l ? ? l h h h l h l ? ? h l h ? ? h l h
mc10e136, mc100e136 http://onsemi.com 8 figure 4. programmable divider waveforms s1 cout c lock divide by 37 load 000000 000001 000010 000011 100010 100011 100100 ??? ??? ??? load the exercise of building a programmable divider then becomes simply determining what value to load into the counter to accomplish the desired division. since the load operation requires a clock pulse, to divide by n, n1 must be loaded into the counter. a single e136 device is capable of divide ratios of 2 to 64 inclusive, table 1 outlines the load values for the various divide ratios. figure 4 presents the waveforms resulting from a divide by 37 operation. note that the availability of the cout complimentary output cout allows the user to choose the polarity of the divide by output. for single device programmable counters the e016 counter is probably a better choice than the e136. the e016 has an internal feedback to control the reloading of the counter, this not only simplifies board design but also will result in a faster maximum count frequency. for programmable dividers of larger than 8 bits the superiority of the e016 diminishes, and in fact for very wide dividers the e136 will provide the capability of a faster count frequency. this potential is a result of the cascading features mentioned previously in this document. figure 5 shows the architecture of a 24-bit programmable divider implemented using e136 counters. note the need for one external gate to control the loading of the entire counter chain. an ideal device for the external gating of this architecture would be the 4-input or function in the 8-lead soic eclinps lite ? family. however the final decision as to what device to use for the external gating requires a balancing of performance needs, cost and available board space. note that because of the need for external gating the maximum count frequency of a given sized programmable divider will be less than that of a single cascaded counter. figure 5. 24-bit programmable divider architecture s1 s1 s1 s1 q0 > q5 d0 > d5 clk q0 > q5 d0 > d5 clk q0 > q5 d0 > d5 clk lsb q0 > q5 d0 > d5 clout cout clin cin clk clock aloo aloo aloo clout cout clin cin clout cout clin cin msb clout cout clin cin out
mc10e136, mc100e136 http://onsemi.com 9 figure 6. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e136, mc100e136 http://onsemi.com 10 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
mc10e136, mc100e136 http://onsemi.com 11 notes
mc10e136, mc100e136 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e136/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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